1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the management and manipulation of operands of different bit widths that have zero values added to form register values of a constant bit-width.
2. Description of the Prior Art
It is known to provide data processing systems that manipulate operands (source operands or destination operands) that have different bit-widths, such as single word operands (SW), double word operands (DW) and quad word operands (QW). Operands of these different bit widths may be stored within registers that have a constant bit-width, such as the width of a quad word. In some of these systems it is architecturally defined that when an operation of less than the register bit-width is written in to a register then it is prefixed with zero values filling the unused high-order portion of the register such that the full register is occupied with defined bit values. As an example, a 32-bit single word may be stored using a 128-bit register within the least significant 32-bits of that register and the remaining 96-bits of that register filled with zero values such that the entire 128-bit register is filled.
One possible way of achieving this type of operation is to add the zero bits to the operand whenever the operand is written in to a register and arrange all the registers to be of the constant maximum size, e.g. all the registers may be 128-bit registers capable of storing a full quad word operand as well as storing double word operands and single word operands that are prefixed with an appropriate number of zero values. However, a disadvantage with this approach is that a larger amount of physical overhead is required to store all of the zero values which effectively contain no useful information. Furthermore, energy is consumed in pushing these zero values along the data path of the processor system. In a system such as an out-of-order processor using register renaming, the physical registers used to store operands and for which mappings are held relating the physical registers to architectural registers represent a finite resource. Accordingly, inefficient use of the physical register resources provided can constrain the degree of out-of-order processing which may be achieved and the amount of speculation which may be supported.